2MB
  • Product pinout
  • Description
  • AT61162E,AT61162E
  • The AT61162E is a Rad Hard module, highly-integrated and very low-power CMOS static RAM organized as 2M x 8 bits. It is organized with 16 banks of 1 Mbit. Each bank has a 8-bit interface and is selected with 16 specific CS: 0 - 15. Banks are selectable by ...
  • CY7C1320JV18,18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses ...
  • CY7C1321CV18,18-Mbit DDR-II SRAM 4-Word Burst Architecture
  • The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses ...
  • CY62167EV18,16-Mbit (1M X 16) Static RAM
  • The CY62167EV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This , is ideal for providing More Battery Life, (MoBL ) in portable applications ...
  • CY7C1069DV33,16-Mbit (2M X 8) Static RAM
  • The CY7C1069DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 8 bits. To write to the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO through IO ) is then ...
  • CY7C1315CV18,18-Mbit QDR?-II SRAM 4-Word Burst Architecture
  • The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The ...
  • CY62167EV30,16-Mbit (1M X 16 / 2M X 8) Static RAM
  • The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits/2M words by 8 bits. This device features an advanced circuit design designed to provide an ultra low active current. Ultra low active current is ideal for , providing ...
  • CY7C1314CV18,18-Mbit QDR-II SRAM 2-Word Burst Architecture
  • The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18, and CY7C1314CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The ...
  • CY7C1320CV18,18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses ...
  • CY7C1314BV18,18-Mbit QDR?-II SRAM 2 Word Burst Architecture
  • The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated Data Outputs ...
  • CY62168EV30,16-Mbit (2M X 8) Static RAM
  • The CY62168EV30 is a high performance CMOS static RAM organized as 2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. , This is ideal for providing More Battery Life, (MoBL ) in portable applications ...
  • CY62167E,16-Mbit (1M X 16 / 2M X 8) Static RAM
  • The CY62167E is a high performance CMOS static RAM organized as 1M words by 16 bits/2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life, , (MoBL ) in ...
  • CY7C1383DV25,18-Mbit (512K X 36/1M X 18) Flow-Through SRAM
  • The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/ CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 ...
  • CY7C1382DV25,18-Mbit (512K X 36/1M X 18) Pipelined SRAM
  • The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers ...
  • CY7C1383D,18-Mbit (512K X 36/1M X 18) Flow-Through SRAM
  • The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A ...
  • CY7C1382D,18-Mbit (512K X 36/1M X 18) Pipelined SRAM
  • The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers ...
  • CY62168DV30,? 16-Mbit (2M X 8) MoBL Static RAM
  • The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. , This is ideal for providing More Battery Life, (MoBL ) in portable ...
  • CY62167DV30,16-Mbit (1M X 16) Static RAM
  • The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. ...
  • CYU01M16SFE,16-Mbit (1M X 16) Pseudo Static RAM
  • The CYU01M16SFE is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. ...
  • CYU01M16SCG,16-Mbit (1M X 16) Pseudo Static RAM
  • The CYU01M16SCG is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. ...
  • CY7C1320BV18,18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses ...
  • CY7C1313BV18,18-Mbit QDR?-II SRAM 4-Word Burst Architecture
  • The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs ...
  • CY7C1393BV18,18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read ...
  • CYK001M16SCCA,16-Mbit (1M X 16) Pseudo Static RAM
  • The CYK001M16SCCA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for ...
  • CYK001M16ZCCA,16-Mbit (1M X 16) Pseudo Static RAM
  • The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active , current. This is ideal for ...
  • CY7C1312AV18,18-Mb QDR?-II SRAM 2-Word Burst Architecture
  • The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read ...
  • K1S16161CA,1M X 16 Bit Page Mode Uni-Transistor CMOS RAM
  • The K1S16161CA is fabricated by SAMSUNG advanced CMOS technology using one transistor memory cell. The device support 4 page mode operation, Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also ...
  • K7S1636T4C,18Mb QDRII+ SRAM Specification
  • The K7S1636T4C and K7S1618T4C are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7S1636T4C and 1,048,576 words by 18 bits for K7S1618T4C. The QDR operation is possible by supporting ...
  • K7S1618T4C,18Mb QDRII+ SRAM Specification
  • The K7S1636T4C and K7S1618T4C are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7S1636T4C and 1,048,576 words by 18 bits for K7S1618T4C. The QDR operation is possible by supporting ...
  • K7R161882B,18Mb QDRII SRAM Specification
  • The K7R163682B,K7R161882B and K7R160982B are 18,874,368-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7R163682B, 1,048,576 words by 18 bits for K7R161882B and 2,097,152 words by 9bits for ...
  • K7R160982B,18Mb QDRII SRAM Specification
  • The K7R163682B,K7R161882B and K7R160982B are 18,874,368-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7R163682B, 1,048,576 words by 18 bits for K7R161882B and 2,097,152 words by 9bits for ...
  • K7R163684B,18Mb QDRII SRAM Specification
  • The K7R163684B and K7R161884B are 18,874,368-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7R163684B and 1,048,576 words by 18 bits for K7R161884B. ...
  • K7R161884B,18Mb QDRII SRAM Specification
  • The K7R163684B and K7R161884B are 18,874,368-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7R163684B and 1,048,576 words by 18 bits for K7R161884B. ...
  • K7Q163662B,TM 512Kx36-bit, 1Mx18-bit QDR SRAM
  • The K7Q163662B and K7Q161862B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163662B and 1,048,576 words by 18 bits for K7Q161862B. The QDR operation is possible by supporting ...
  • K7Q161862B,TM 512Kx36-bit, 1Mx18-bit QDR SRAM
  • The K7Q163662B and K7Q161862B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163662B and 1,048,576 words by 18 bits for K7Q161862B. The QDR operation is possible by supporting ...
  • K7Q163664B,TM 512Kx36 & 1Mx18 QDR B4 SRAM
  • The K7Q163664B and K7Q161864B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163654B and 1,048,576 words by 18 bits for K7Q161864B. ...
  • K7Q161864B,TM 512Kx36 & 1Mx18 QDR B4 SRAM
  • The K7Q163664B and K7Q161864B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163654B and 1,048,576 words by 18 bits for K7Q161864B. ...
  • K7K1636T2C,18Mb DDRII+ SRAM Specification
  • The K7K1636T2C and K7K1618T2C are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7K1636T2C and 1,048,576 words by 18 bits for K7K1618T2C . Address, data inputs, and all control signals are ...
  • K7K1618T2C,18Mb DDRII+ SRAM Specification
  • The K7K1636T2C and K7K1618T2C are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7K1636T2C and 1,048,576 words by 18 bits for K7K1618T2C . Address, data inputs, and all control signals are ...
  • K7I163682B,18Mb DDRII SRAM Specification
  • The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B. ...
  • K7I161882B,18Mb DDRII SRAM Specification
  • The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B. ...
  • K7I163684B,18Mb DDRII SRAM Specification
  • The K7I163684B and K7I161884B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7I163684B and 1,048,576 words by 18 bits for K7I161884B. ...
  • K7I161884B,18Mb DDRII SRAM Specification
  • The K7I163684B and K7I161884B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7I163684B and 1,048,576 words by 18 bits for K7I161884B. ...
  • K7J163682B,18Mb DDRII SRAM Specification
  • The K7J163682B and K7J161882B are 18,874,368-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7J163682B and 1,048,576 words by 18 bits for K7J161882B. ...
  • K7J161882B,18Mb DDRII SRAM Specification
  • The K7J163682B and K7J161882B are 18,874,368-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7J163682B and 1,048,576 words by 18 bits for K7J161882B. ...
  • K7D163674B,16M DDR SYNCHRONOUS SRAM
  • The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung\'s advanced CMOS technology. ...
  • K7P323688M,32Mb M-die LW SRAM Specification
  • The K7P323688M and K7P321888M are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology. Single differential HSTL level K clocks are ...
  • K7P163666A,512Kx36 & 1Mx18 Synchronous Pipelined SRAM
  • The K7P163666A and K7P161866A are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36 bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology. Single differential HSTL level K clocks are ...
  • K7P803611B,256Kx36 & 512Kx18 Synchronous Pipelined SRAM
  • The K7P803611B and K7P801811B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7P803611B and 524,288 words by 18 bits for K7P801811B, fabricated using Samsung\'s advanced CMOS technology. ...
  • K7P801866B,256Kx36 & 512Kx18 Synchronous Pipelined SRAM
  • The K7P803666B and K7P801866B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7P803666B and 524,288 words by 18 bits for K7P801866B, fabricated using Samsung\'s advanced CMOS technology. ...
  • K7B163635B,18Mb Sync. Burst SRAM Specification
  • The K7B163635B and K7B161835B are 18,874,368-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and ...
  • K7A163631B,18Mb B-die Sync. SRAM Specification
  • The K7A163631B and K7A161831B are 18,874,368-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and ...
  • K7A163630B,18Mb Sync. Pipelined Burst SRAM Specification
  • The K7A163630B and K7A161830B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and inte- grates address and ...
  • K7A161830B,18Mb Sync. Pipelined Burst SRAM Specification
  • The K7A163630B and K7A161830B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and inte- grates address and ...
  • K7B161835B,512Kx36 & 1Mx18 Synchronous SRAM
  • The K7B163635B and K7B161835B are 18,874,368-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. ...
  • K7B161825A,512Kx36 & 1Mx18 Synchronous SRAM
  • The K7B163625A and K7B161825A are 18,874,368-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and inte- grates address ...
  • K7A161800A,16Mb Sync. Pipelined SRAM Specification
  • The K7A163600A and K7A161800A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and integrates address and ...
  • K7M163635B,512Kx36 & 1Mx18-Bit Flow Through NtRAM
  • The K7M163635B and K7M161835B are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7M161835B,512Kx36 & 1Mx18-Bit Flow Through NtRAM
  • The K7M163635B and K7M161835B are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7M163625A,512Kx36 & 1Mx18-Bit Flow Through NtRAM
  • The K7M163625A and K7M161825A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7M161825A,512Kx36 & 1Mx18-Bit Flow Through NtRAM
  • The K7M163625A and K7M161825A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N163631B,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163631B and K7N161831B are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N161831B,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163631B and K7N161831B are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N163645A,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163645A and K7N161845A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N161845A,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163645A and K7N161845A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N163601A,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163601A and K7N161801A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N161801A,512Kx36 & 1Mx18-Bit Pipelined NtRAM
  • The K7N163601A and K7N161801A are 18,874,368-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7Z167288B,512Kx36 & 256Kx72-Bit DLW(Dobule Late Write) RAM
  • The K7Z163688B & K7Z167288B is 18,874,368-bits Synchro- nous Static SRAMs. The Double Late Write RAM utilizes all the bandwidth in any com- bination of operating cycles. Address, data inputs, and all control signals except EP2, EP3, and SD are ...
  • IS61WV20488ALL,2M X 8 HIGH-SPEED CMOS STATIC RAM
  • The ISSI IS61WV20488ALL IS61WV20488BLL and IS64WV20488BLL are very high-speed, low power, 2M-word by 8-bit CMOS static RAM. The IS61WV20488ALL/BLL and IS64WV20488BLL are fabricated using ISSI\'s high- performance CMOS technology. This highly ...
  • IS62WV20488ALL,2M X 8 HIGH-SPEED LOW POWER CMOS STATIC RAM
  • The ISSI IS62WV20488ALL IS62WV20488BLL is a high-speed, low power, 2M-word by 8-bit CMOS static RAM. The IS62WV20488ALL IS62WV20488BLL is fabricated using ISSI\'s high- performance CMOS technology. This highly reliablee process coupled with ...
  • IS64WV20488,2M X 8 HIGH-SPEED CMOS STATIC RAM
  • The ISSI IS61WV20488ALL/BLL and IS64WV20488BLL are very high-speed, low power, 2M-word by 8-bit CMOS static RAM. The IS61WV20488ALL/BLL and IS64WV20488BLL are fabricated using ISSI\'s high- performance CMOS technology. This highly reliable process ...