MONOLITHIC MANCHESTER DECODER

The 3D7502 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level, embedded-clock signal. In this encoding mode, a Logic one is represented by a high-to-low transition within the bit cell, while a Logic zero is represented by a low-to-high transition. The recovered Clock and data signals are presented on CLK and DATB, respectively, with By Data Delay Devices, Inc.