Dual JK Positive Edge-Triggered Flip-Flop

The 54AC109 consists of two high-speed completely independent transition clocked JK# Flip-Flops The clocking operation is independent of rise and fall times of the Clock waveform. The JK# design allows operation as a D Flip-Flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K# inputs together.
Asynchronous Inputs:
LOW input to S#D (Set) sets Q to HIGH level
LOW input to C#D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C#D and S#D makes both Q and Q#
By National Semiconductor Corporation
Part Manufacturer Description Datasheet Samples
CD54AC109F3A Texas Instruments Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125
54AC109 's Packages54AC109 's pdf datasheet



54AC109 Pinout, Pinouts
54AC109 pinout,Pin out
This is one package pinout of 54AC109,If you need more pinouts please download 54AC109's pdf datasheet.

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