Octal D Flip-Flop With Clock Enable

The 54AC377 has eight edge-triggered, D-type Flip-Flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all Flip-Flops simultaneously, when the Clock Enable (CE#) is LOW.
The Register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH Clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH Clock transition for predictable operation.
By National Semiconductor Corporation
54AC377 's Packages54AC377 's pdf datasheet



54AC377 Pinout, Pinouts
54AC377 pinout,Pin out
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