18-bit Bus Interface D-type Flip-flop With Reset And Enable 3-state - Nxp Semiconductors

The 74ABT16823A 18-bit bus Interface Register is designed to eliminate the extra packages required to Buffer existing Registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16823A has two 9-bit wide buffered Registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The Registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High Clock transition is transferred to the corresponding Flip-Flops Q output. Two options are available, 74ABT16823A which does not have the bus-hold feature and 74ABTH16823A which incorporates the bus-hold feature. By NXP Semiconductors
74ABTH16823A 's Packages74ABTH16823A 's pdf datasheet



74ABTH16823A Pinout, Pinouts
74ABTH16823A pinout,Pin out
This is one package pinout of 74ABTH16823A,If you need more pinouts please download 74ABTH16823A's pdf datasheet.

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