74AHC273; 74AHCT273 Octal D-type Flip-flop With Reset; Positive-edge Trigger

The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type Flip-Flops with individual D inputs and Q outputs. The common Clock (CP) and master reset (MR) inputs load and reset (clear) all Flip-Flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH Clock transition, is transferred to the corresponding output (Qn) of the Flip-Flop All outputs will be forced LOW independently of Clock or data inputs by a LOW on the MR input. The device is useful for applications where the true output only is required and the Clock and master reset are common to all storage elements.
By NXP Semiconductors
74AHC273BQ 's Packages74AHC273BQ 's pdf datasheet
74AHC273D SO
74AHC273PW TSSOP
74AHCT273BQ DHVQFN
74AHCT273D SO
74AHCT273PW TSSOP




74AHC273BQ Pinout, Pinouts
74AHC273BQ pinout,Pin out
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