Octal D Flip-flop With Enable

The 74ALS377 has eight edge-triggered D-type Flip-Flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all Flip-Flops simultaneously when the Enable (E) is Low. The Register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High Clock transition, is transferred to the corresponding Flip-Flops Q output. The E input must be stable one setup time prior to the Low-to-High Clock transition for predictable operation. By NXP Semiconductors
74ALS377 's Packages74ALS377 's pdf datasheet



74ALS377 Pinout, Pinouts
74ALS377 pinout,Pin out
This is one package pinout of 74ALS377,If you need more pinouts please download 74ALS377's pdf datasheet.

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