74AUP1G175 Low-power D-type Flip-flop With Reset; Positive-edge Trigger

The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt Trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G175 is a single positive-edge triggered D-type Flip-Flop with individual data (D) input, Clock (CP) input, master reset (MR) input, and Q output.The master reset (MR) is an asynchronous active LOW input and operates independently of the Clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the Clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH Clock transition, for predictable operation.
By NXP Semiconductors
74AUP1G175 's Packages74AUP1G175 's pdf datasheet

74AUP1G175 Pinout, Pinouts
74AUP1G175 pinout,Pin out
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