74AUP2G240 Low-power Dual Inverting Buffer/line Driver; 3-stateThe 74AUP2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt Trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF .
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP2G240 provides the dual inverting Buffer Line Driver with 3-state output. The
3-state output is controlled by the output enable input (nOE). A high level at pin nOE
causes the output to assume a high-impedance OFF-state.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input nOE is high.
By NXP Semiconductors |
Part | Manufacturer | Description | Datasheet | Samples | |
---|---|---|---|---|---|
SN74AUP2G240DCUR | Texas Instruments | Low-Power Dual Buffer/Driver With 3-State Outputs 8-VSSOP -40 to 85 | |||
SN74AUP2G240RSER | Texas Instruments | Low-Power Dual Buffer/Driver With 3-State Outputs 8-UQFN -40 to 85 | |||
SN74AUP2G240YFPR | Texas Instruments | Low-Power Dual Buffer/Driver With 3-State Outputs 8-DSBGA -40 to 85 | |||
SN74AUP2G240DQER | Texas Instruments | Low-Power Dual Buffer/Driver With 3-State Outputs 8-X2SON -40 to 85 |
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74AUP2G240 Pb-Free | 74AUP2G240 Cross Reference | 74AUP2G240 Schematic | 74AUP2G240 Distributor |
74AUP2G240 Application Notes | 74AUP2G240 RoHS | 74AUP2G240 Circuits | 74AUP2G240 footprint |