74AUP2G240 Low-power Dual Inverting Buffer/line Driver; 3-state

The 74AUP2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt Trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF . The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP2G240 provides the dual inverting Buffer Line Driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A high level at pin nOE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is high.
By NXP Semiconductors