74F113 Dual J-K Negative Edge-triggered Flip-flops Without Reset

The 74F113 dual negative edge-triggered JK-type Flip-Flop features individual J, K, Clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs.A high level on the Clock (CP) input enables the J and K inputs and data will be accepted. The Logic levels at the J and K inputs may be allowed to change while the CP is high and Flip-Flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.
By NXP Semiconductors
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74F113 Pinout, Pinouts
74F113 pinout,Pin out
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