74F173 Quad D-type Flip-flop (3-State)

The 74F173 is a high speed 4,bit parallel load Register with Clock enable control, 3,state buffered outputs, and master reset (MR). When the two Clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the Register simultaneously with low,to,high Clock (CP) transition. When one or both enable inputs are high one setup time before the low,to,high Clock transition, the Register retains the previous data.Data inputs and Clock enable inputs are fully edge,triggered and must be stable only one setup time before the low,to,high Clock transition.The master reset (MR) is an active,high asynchronous input. When the MR is high, all four flip,flops are reset (cleared) independently of any other input condition.The 3,state output Buffers are controlled by a 2,input NOR Gate When both output enable (OE0 and OE1) inputs are low, the data in the Register is presented at the Q output.When one or both OE inputs are high, the outputs are forced to a high impedance ,off, state.The 3,state output Buffers are completely independent of the Register operation; the OE transition does not affect the Clock and reset operations.
By NXP Semiconductors
74F173 's Packages74F173 's pdf datasheet

74F173 Pinout, Pinouts
74F173 pinout,Pin out
This is one package pinout of 74F173,If you need more pinouts please download 74F173's pdf datasheet.

74F173 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

74F173 Pb-Free 74F173 Cross Reference 74F173 Schematic 74F173 Distributor
74F173 Application Notes 74F173 RoHS 74F173 Circuits 74F173 footprint
Hot categories