74F50729 Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics

The 74F50729 is a dual positive edge-triggered D-type featuring individual data, Clock set and reset inputs; also true and complementary outputs. The 74F50729 is designed so that the outputs CAN never Display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or Display a metastable state. Typical metastability parameters for the 74F50729 are: = 135 ps and To = 9.8 , 106 sec, where represents a function of the rate at which a latch in a metastable state resolves that condition, and To represents a function of the measurement of the propensity of a latch to enter a metastable state. Set (SDn) and reset (RDn) are asynchronous positive-edge triggered inputs and operate independently of the Clock (CPn) input. Data must be stable just one setup time prior to the low-to-high transition of the Clock for guaranteed propagation delays. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.
By NXP Semiconductors
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74F50729 Pinout, Pinouts
74F50729 pinout,Pin out
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