74F552 Octal Registered Transceiver With Parity And Flags (3-State)

The 74F522 Octal Registered Transceiver contains two 8-bit Registers for temporary storage of data flowing in either direction. Each Register has its own Clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag Flip-Flop that is set automatically as the Register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each Register has a separate Output Enable (OEAS, OEBR) for its 3-State Buffer The separate Clocks Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A port to the B port, a parity bit is generated. On the other hand, when data is transferred from the B port to the A port, the parity of input data on B0,B7 is checked.
By NXP Semiconductors
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74F552 Pinout, Pinouts
74F552 pinout,Pin out
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