Quad 64-bit Static Shift Register

The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT7731 are quad 64-bit static Shift registers with a recycling mode. Each Register has separate data inputs Da to DD Clock inputs CP to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transitio of the Clock pulse. Each recycling mode input controls two Registers RECab for Registers A and B and RECcd for Registers C and D. When the REC input is HIGH, the device i in the recycling mode and data at th output is shifted back into the input the Register so after 64 Clock pulse the contents of a Register is again in its original position. This enables th user to tap off data from any positio When the REC input is LOW extern data CAN be shifted in. By NXP Semiconductors
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74HC-HCT7731-CNV 's Packages74HC-HCT7731-CNV 's pdf datasheet

74HC-HCT7731-CNV Pinout, Pinouts
74HC-HCT7731-CNV pinout,Pin out
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