Dual JK Flip-flop With Reset; Negative-edge Trigger

The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type Flip-Flops featuring individual J, K, Clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. By NXP Semiconductors
Part Manufacturer Description Datasheet Samples
CD74HCT107EE4 Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125
CD74HCT107E Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125
74HCT107 's Packages74HCT107 's pdf datasheet



74HCT107 Pinout, Pinouts
74HCT107 pinout,Pin out
This is one package pinout of 74HCT107,If you need more pinouts please download 74HCT107's pdf datasheet.

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