74HC193; 74HCT193 Presettable Synchronous 4-bit Binary Up, Down Counter

The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down Counters Separate up/down Clocks CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either Clock input. If the CPU Clock is pulsed while CPD is held HIGH, the device will count up. If the CPD Clock is pulsed while CPU is held HIGH, the device will count down. Only one Clock input CAN be held HIGH at any time, or erroneous operation will result. The device CAN be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The 74HC193 and 74HCT193 each contain four master-slave JK Flip-Flops with the necessary steering Logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each Flip-Flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. One Clock should be held HIGH while counting with the other, otherwise the circuit will either count by twos or not at all, depending on the state of the first Flip-Flop which cannot toggle as long as either Clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating Clock is HIGH to avoid erroneous counts. The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up Clock Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs CAN be used as the Clock input signals to the next higher order circuit in a multistage Counter since they duplicate the Clock waveforms. Multistage Counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The Counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the Counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the Clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load Gates override both Clock inputs and set all outputs (Q0 to Q3) LOW. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted.
By NXP Semiconductors
Part Manufacturer Description Datasheet Samples
CD74HCT193E Texas Instruments High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters with Asynchronous Reset 16-PDIP -55 to 125
CD74HCT193EE4 Texas Instruments High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters with Asynchronous Reset 16-PDIP -55 to 125
74HCT193 's Packages74HCT193 's pdf datasheet
74HC193D SO
74HC193N DIP
74HCT193D SO

74HCT193 Pinout, Pinouts
74HCT193 pinout,Pin out
This is one package pinout of 74HCT193,If you need more pinouts please download 74HCT193's pdf datasheet.

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