74LV175 Quad D-type Flip-flop With Reset; Positive-edge Trigger

The 74LV175 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT175. The 74LV175 has four edge-triggered, D-type Flip-Flops with individual D inputs and both Q and Q outputs. The common Clock (CP) and master reset (MR) inputs load and reset (clear) all Flip-Flops simultaneously. The Register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH Clock transition, is transferred to the corresponding output (Qn) of the Flip-Flop All Qn outputs will be forced LOW independently of Clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and complement outputs are required and the Clock and master reset are common to all storage elements.
By NXP Semiconductors