74LVC1G00 Single 2-input NAND GateThe 74LVC1G00 provides the single 2-input NAND function.
Input CAN be driven from either 3.3 V or 5 V devices. These features allow the use of these
devices in a mixed 3.3 V and 5 V environment.
Schmitt Trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
By NXP Semiconductors |
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| 74LVC1G00 Pb-Free | 74LVC1G00 Cross Reference | 74LVC1G00 Schematic | 74LVC1G00 Distributor |
| 74LVC1G00 Application Notes | 74LVC1G00 RoHS | 74LVC1G00 Circuits | 74LVC1G00 footprint |
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