74LVC595A 8-bit Serial-in/serial-out Or Parallel-out Shift Register; 3-state

The 74LVC595A is an 8-bit serial-in/serial or parallel-out Shift register with a storage Register and 3-state outputs. Both the shift and storage Register have separate Clocks The input CAN be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift Register is transferred to the storage Register on a positive-going transition of the STCP input. If both Clocks are connected together, the Shift register will always be one Clock pulse ahead of the storage Register The Shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift Register stages. The storage Register has 8 parallel 3-state bus driver outputs. Data in the storage Register appears at the output whenever the output enable input (OE) is LOW.
By NXP Semiconductors
74LVC595A 's Packages74LVC595A 's pdf datasheet
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74LVC595AD SO
74LVC595APW TSSOP




74LVC595A Pinout, Pinouts
74LVC595A pinout,Pin out
This is one package pinout of 74LVC595A,If you need more pinouts please download 74LVC595A's pdf datasheet.

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