Low Voltage IEEE 161284 Translating Transceiver

The LVX161284 contains eight bidirectional data Buffers and eleven control/status Buffers to implement a full IEEE 1284 compliant Interface The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side).
Outputs on the cable side CAN be configured to be either open drain or high drive ( 14 mA) and are connected to a separate power supply pin (VCC-cable) to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCC-cable supply to provide proper termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive CMOS outputs designed to Interface with 3V Logic The DIR input controls data flow on the A1-A8/B1-B8 transceiver pins.
By Fairchild Semiconductor
74LVX161284 's Packages74LVX161284 's pdf datasheet

74LVX161284 Pinout, Pinouts
74LVX161284 pinout,Pin out
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