25-Bit Configurable Registered Buffer W/Address-Parity Test

This 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET
By Texas Instruments
Part Manufacturer Description Datasheet Samples
74SSTUB32866AZKER Texas Instruments 25-Bit Configurable Registered Buffer w/Address-Parity Test 96-LFBGA -40 to 85
74SSTUB32866A 's Packages74SSTUB32866A 's pdf datasheet
74SSTUB32866AZKER LFBGA




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