8MB
  • Product pinout
  • Description
  • CY7C1515JV18,72-Mbit QDR?-II SRAM 4-Word Burst Architecture
  • The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The ...
  • CY7C1523AV18,72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to ...
  • CY7C1515AV18,72-Mbit QDR?-II SRAM 4-Word Burst Architecture
  • The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The ...
  • CY7C1514AV18,72-Mbit QDR-II SRAM 2-Word Burst Architecture
  • The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The ...
  • CY7C1520AV18,72-Mbit DDR-II SRAM 2-Word Burst Architecture
  • The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses ...
  • CY7C1485V33,72-Mbit (2M X 36/4M X 18) Pipelined DCD Sync SRAM
  • The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered ...
  • CY7C1485V25,72-Mbit (2M X 36/4M X 18) Pipelined DCD Sync SRAM
  • The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered ...
  • CY7C1484V33,72-Mbit (2M X 36/4M X 18) Pipelined DCD Sync SRAM
  • The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered ...
  • CY7C1520V18,72-Mbit DDR-II SRAM 2-Word Burst Architecture
  • The CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for ...
  • CY7C1515V18,72-Mbit QDR?- II SRAM 4-Word Burst Architecture
  • The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to ...
  • CY7C1514V18,72-Mbit QDR-II? SRAM 2-Word Burst Architecture
  • The CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to ...
  • CY7C1484V25,72-Mbit (2M X 36/4M X 18) Pipelined DCD Sync SRAM
  • The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered ...
  • K1B6416B2D,64Mb (4M X 16 Bit) UtRAM
  • The world is moving into the mobile multi-media era and therefore the mobile handsets need bigger & faster memory capacity to handle the multi-media data. SAMSUNGs UtRAM products are desgned to meet all the request from the various customers who want to cope ...
  • K1B6416B8D,64Mb (4M X 16 Bit) UtRAM
  • The world is moving into the mobile multi-media era and therefore the mobile handsets need bigger & faster memory capacity to handle the multi-media data. SAMSUNGs UtRAM products are desgned to meet all the request from the various customers who want to cope ...
  • K7R643682M,72Mb QDRII SRAM Specification
  • The K7R643682M,K7R641882M and K7R640982M are 75,497,472-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7R643682M, 4,194,304 words by 18 bits for K7R641882M and 8,388,608 words by 9bits for ...
  • K7R641882M,72Mb QDRII SRAM Specification
  • The K7R643682M,K7R641882M and K7R640982M are 75,497,472-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7R643682M, 4,194,304 words by 18 bits for K7R641882M and 8,388,608 words by 9bits for ...
  • K7R640982M,72Mb QDRII SRAM Specification
  • The K7R643682M,K7R641882M and K7R640982M are 75,497,472-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7R643682M, 4,194,304 words by 18 bits for K7R641882M and 8,388,608 words by 9bits for ...
  • K7R643684M,TM 2Mx36-bit, 4Mx18-bit QDR II B4 SRAM
  • The K7R643684M and K7R641884M are 75,497,472-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7R643684M and 4,194,304 words by 18 bits for K7R641884M. The QDR operation is possible by supporting ...
  • K7R641884M,72Mb QDRII SRAM Specification
  • The K7R643684M and K7R641884M are 75,497,472-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7R643684M and 4,194,304 words by 18 bits for K7R641884M. The QDR operation is possible by supporting ...
  • K7I643682M,72Mb DDRII SRAM Specification
  • The K7I643682M and K7I641882M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643682M and 4,194,304 words by 18 bits for K7I641882M. Address, data inputs, and all control signals ...
  • K7I641882M,72Mb DDRII SRAM Specification
  • The K7I643682M and K7I641882M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643682M and 4,194,304 words by 18 bits for K7I641882M. Address, data inputs, and all control signals ...
  • K7I643684M,72Mb DDRII SRAM Specification
  • The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M. Address, data inputs, and all control signals ...
  • K7I641884M,72Mb DDRII SRAM Specification
  • The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M. ...
  • K7J643682M,72Mb DDRII SRAM Specification
  • The K7J643682M and K7J641882M are 75,497,472-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7J643682M and 4,194,304 words by 18 bits for K7J641882M. The DDR SIO operation is possible by ...
  • K7J641882M,72Mb DDRII SRAM Specification
  • The K7J643682M and K7J641882M are 75,497,472-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7J643682M and 4,194,304 words by 18 bits for K7J641882M. ...
  • K7N643645M,2Mx36 & 4Mx18-Bit Pipelined NtRAM
  • The K7N643645M and K7N641845M are 75,497,472-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
  • K7N641845M,2Mx36 & 4Mx18-Bit Pipelined NtRAM
  • The K7N643645M and K7N641845M are 75,497,472-bits Syn- chronous Static SRAMs. TM The NtRAM , or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except ...
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