2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAMThe A67L16181 A67L06361 SRAMs integrate a 2M X 18,
1M X 36 SRAM core with advanced synchronous peripheral
circuitry and a 2-bit burst Counter These SRAMs are
optimized for 100 percent bus utilization without the insertion
of any wait cycles during Write-Read alternation. The positive
edge triggered single Clock input (CLK) controls all
synchronous inputs passing through the Registers The
synchronous inputs include all address, all data inputs, active
low chip enable (CE), two additional chip enables for easy
depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ),
synchronous Clock enable ( CEN ), byte write enables
(BW1,BW2 ,BW3 ,BW4 ) and read/write (R/W). By AMIC Technology Corporation
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A67L16181 Pb-Free | A67L16181 Cross Reference | A67L16181 Schematic | A67L16181 Distributor |
A67L16181 Application Notes | A67L16181 RoHS | A67L16181 Circuits | A67L16181 footprint |