1m X 18, 512k X 36 Lvttl, Pipelined Zebl Sram

The AMIC Zero Bus Latency (ZeBLTM) SRAM family A67P0618E A67P9336E employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P0618 A67P9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst Counter These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single Clock input (CLK) controls all synchronous inputs passing through the Registers The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous Clock enable ( CEN), byte write enables (BW1,BW2 ,BW3 ,BW4 ) and read/write (R/W). Asynchronous inputs include the output enable (OE), Clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode CAN provide either interleaved or linear operation, burst operation CAN be initiated by synchronous address Advance/Load (ADV/LD) pin in Low state. Subsequent burst address CAN be internally generated by the chip and controlled by the same input pin ADV/LD in High state. By AMIC Technology Corporation