1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM

The A67P0618, A67P9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst Counter These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single Clock input (CLK) controls all synchronous inputs passing through the Registers The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous Clock enable ( CEN), byte write enables (BW1,BW2 ,BW3 ,BW4 ) and read/write (R/W). By AMIC Technology Corporation