256k X 18, 128k X 36 Lvttl, Flow-through Zebl Sram

The AMIC Zero Bus Latency (ZeBLTM) SRAM family A67P83181E A67P73361E employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P83181, A67P73361 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst Counter These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single Clock input (CLK) controls all synchronous inputs passing through the Registers The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), cycle start input (ADV/ LD ), synchronous Clock enable ( CEN), byte write enables ( BW1 , BW2 , BW3 , BW4 ) and read/write (R/W). By AMIC Technology Corporation
A67P73361 's PackagesA67P73361 's pdf datasheet
A67P83181E
A67P73361E
A67P83181E-7.5
A67P83181E-7.5F
A67P83181E-8.5
A67P83181E-8.5F
A67P83181E-10.0
A67P83181E-10.0F
A67P73361E-7.5
A67P73361E-7.5F
A67P73361E-8.5
A67P73361E-8.5F
A67P73361E-10.0
A67P73361E-10.0F




A67P73361 Pinout, Pinouts
A67P73361 pinout,Pin out
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