Radiation Hardened Edac (error Detection And Correction Circuit)

The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modied Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are agged and corrected. Single bit errors in check words are agged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle. The ACS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K sufx) or a 28 Lead Ceramic Dual-In-Line Package (D sufx). By Intersil Corporation