Data Retiming Phase Locked Loop - Analog Devices

The AD805 is a data retiming phase-locked loop designed for use with a Voltage-Controlled Crystal Oscillator (VCXO) to perform Clock recovery and data retiming on Nonreturn to Zero (NRZ) data. The circuit provides Clock recovery and data retiming on standard telecommunications STS-3 or STM-1 data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit is used with the AD805 for specification purposes. Similar circuit performance CAN be obtained using other commercially available VCXO circuits. The AD805-VCXO circuit used for Clock recovery and data retiming CAN also be used for large factor frequency multiplication. The AD805-VCXO circuit meets or exceeds CCITT G.958 regenerator specifications for STM-I Type A jitter tolerance and STM-1 Type B jitter transfer. The simultaneous Type A, wide- band jitter tolerance and Type B, narrow-band jitter transfer allows the use of the AD805-VCXO circuit in a regenerative application to overcome optical line system interworking limit- ations based on signal retiming using Type A passive tuned device technology such as Surface-Acoustic-Wave (SAW) or dielectric Resonator Filters with Type B active devices such as Phase-Locked Loops (PLLs). By Analog Devices, Inc.
AD805 's PackagesAD805 's pdf datasheet

AD805 Pinout, Pinouts
AD805 pinout,Pin out
This is one package pinout of AD805,If you need more pinouts please download AD805's pdf datasheet.

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