1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision Charge Pump CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.
The Clock Distribution section provides LVPECL outputs and outputs that may be programmed to either LVDs or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.
Each divider allows the user to change the phase of one Clock output relative to another Clock output. This phase select functions as a coarse Timing adjustment. Some outputs also feature programmable delay elements with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.
The AD9510 is ideally suited for Data Converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.
The AD9510 is available in a 64-lead LFCSP and is specified from -40C to +85C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the Charge Pump supply, VCP, to 5.5V.
Applications Low jitter, low phase noise Clock Distribution Clocking high speed ADCs DACs DDs DDC, DUC, MxFE Converters Wireless infrastructure transceivers High performance instrumentation Broadband infrastructure
By Analog Devices, Inc.
AD9510 's PackagesAD9510 's pdf datasheet

AD9510 Pinout, Pinouts
AD9510 pinout,Pin out
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