Low Phase Noise, Fast Settling PLL

ADF4193 consists of a low-noise digital phase frequency detector (PFD), and a precision differential Charge Pump There is also a Differential Amplifier (Diff Amp) to convert the differential Charge Pump output to a single ended voltage for the external voltage controlled Oscillator (VCO). The - based fractional interpolator, working with the N divider, allow programmable modulus fractional-N division. Additionally, the 4-bit reference (R) Counter and on-chip frequency doubler, allows selectable reference signal (REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) CAN be implemented if the synthesizer is used with an external loop Filter and a VCO The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This saves cost, complexity, PCB area, shielding and characterization on previous ping-pong GSM PLL architectures.
By Analog Devices, Inc.
ADF4193 's PackagesADF4193 's pdf datasheet

ADF4193 Pinout, Pinouts
ADF4193 pinout,Pin out
This is one package pinout of ADF4193,If you need more pinouts please download ADF4193's pdf datasheet.

ADF4193 Application circuits
ADF4193 circuits
This is one application circuit of ADF4193,If you need more circuits,please download ADF4193's pdf datasheet.

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