Continuous Rate 12.3Mb/s To 2.7Gb/s Clock And Data Recovery IC

The ADN2865 provides the receiver functions of quantization, signal level detect, and Clock and Data Recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. An integrated deserialiser supports 8 bit parallel transfer to an FPGA or digital ASIC The recovered Clock CAN simultaneously serialize data supplied in an 8 bit parallel format.
The ADN2865 automatically locks to all data rates without the need for an external reference Clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for 40C to +85C ambient temperature, unless otherwise noted.
This device, together with a PIN Diode and a TIA preamplifier, CAN implement a highly integrated, low cost, low power Fiber Optic Receiver
The ADN2865 have many optional features available via an I2C Interface e.g. the user CAN read back the data rate that the ADN2865 is locked on to, or the user CAN set the device to only lock to one particular data rate if provisioning of data rates is required.
Applications Passive Optical Networks SONET OC-1/3/12/48 and all associated FEC rates Fibre Channel, 2 Fibre Channel , GbE, HDTV, etc. WDM transponders Test equipment
By Analog Devices, Inc.
ADN2865 's PackagesADN2865 's pdf datasheet
ADN2865 pdf datasheet download


ADN2865 Pinout, Pinouts
ADN2865 pinout,Pin out
This is one package pinout of ADN2865,If you need more pinouts please download ADN2865's pdf datasheet.

ADN2865 Application circuits
ADN2865 circuits
This is one application circuit of ADN2865,If you need more circuits,please download ADN2865's pdf datasheet.


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