Dual 12-bit 105MSPS ADC With Selectable DDR LVDS Or CMOS Outputs
ADS62P2X is a family of dual channel 12-bit A/D converters with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal Sample and Hold and low jitter Clock Buffer the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that CAN be used to improve SFDR performance at lower full-scale input ranges.
ADS62P2X includes a digital processing block that consists of several useful & commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 & in-built & custom programmable Filters By default, the digital processing block is bypassed & its functions are disabled.
Two output Interface options exist - parallel CMOS and DDR LVDs (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device also supports an external reference mode. The device is specified over the industrial temperature range (-40C to +85C).
By Texas Instruments
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|ADS62P24IRGCTG4||Texas Instruments||Dual 12-bit 105MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85|
|ADS62P24IRGCR||Texas Instruments||Dual 12-bit 105MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85|
|ADS62P24IRGCRG4||Texas Instruments||Dual 12-bit 105MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85|
|ADS62P24EVM||Texas Instruments||ADS62P24 Evaluation Module|
|ADS62P24 Pb-Free||ADS62P24 Cross Reference||ADS62P24 Schematic||ADS62P24 Distributor|
|ADS62P24 Application Notes||ADS62P24 RoHS||ADS62P24 Circuits||ADS62P24 footprint|