2A Sink/Source Bus Termination Regulator

The AP1250CMP is a simple, cost-effective and high-speed linear Regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific Interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The Regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage CAN be pro-grammed by externally forcing the REFEN pin voltage. By APEC
AP1250CMP 's PackagesAP1250CMP 's pdf datasheet

AP1250CMP Pinout, Pinouts
AP1250CMP pinout,Pin out
This is one package pinout of AP1250CMP,If you need more pinouts please download AP1250CMP's pdf datasheet.

AP1250CMP Application circuits
AP1250CMP circuits
This is one application circuit of AP1250CMP,If you need more circuits,please download AP1250CMP's pdf datasheet.

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