2-channel Serial Ata Phy - Atmel Corporation

The AT78C5090 is a 2-channel SATA PHY supporting Gen 1 speeds of 1.5 Gbps. The IP has been designed based on the requirements stated in the Serial ATA Standard, Rev 1.0a, Jan 2003. On the transmit path, parallel data is registered, passed through a transmit FIFO to compensate for phase differences between the link and PHY Clocks 8B/10B encoded and then passed out via a high speed serializer using a spread spectrum Clock Built- in flexibility permits bypassing the encoding block in addition to optionally disabling the spread spectrum clocking. The user CAN control the transmit Buffer output swing and pre-emphasis levels via direct input signals. On the receive path, the AT78C5090 performs the serial-to-parallel conversion, using a high bandwidth Clock and Data Recovery (CDR) block. The recovered data is then passed through a comma alignment block and an optional 8B/10B decode block before being passed to the phyCtrl layer via a parallel Interface This Interface is syn- chronous to the recovered Clock The PHY core has an out of band (OOB) processor. As specified by the Serial ATA standard, three out of band (OOB) signals are used/detected by the PHY namely COMRESET, COMINIT, and COMWAKE. Each of these signals are indicated by a number of bursts of four ALIGN primitives followed by defined idle periods during which the differential voltage on the serial line is null. OOB signals are observed by detecting the temporal spacing between adjacent bursts of activity. Test functions including BIST, scan, parallel and serial loopback modes are configured and controlled by the use of direct input signals. Similarly, error/status bits are indi- cated through direct output signals such as bistErr. By ATMEL Corporation
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