1:9 Differential Clock Driver

The AZ10E111 AZ100E111 is a low skew 1-to-9 differential driver, designed with Clock Distribution in mind. It accepts one signal input, which CAN be either differential or single-ended if the VBB output is used. The signal is fanned-out to 9 identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all QN outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50W, even if only one side is used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. By Unkown
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AZ10E111




AZ100E111 Pinout, Pinouts
AZ100E111 pinout,Pin out
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