ECLinPS 4 Bit D Flip Flop

The AZ10E131 AZ100E131 is a quad master-slave D-type Flip-Flop with differential outputs. Each Flip-Flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE n) inputs for clocking. Common clocking is achieved by holding the CE n inputs LOW and using CC to Clock all four Flip-Flops In this case, the CE n inputs perform the function of controlling the common Clock to each Flip-Flop Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE n are LOW, and transfers to the slave when either CC or CE n (or both) go HIGH. NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established. By Arizona Microtek, Inc.
AZ100E131 's PackagesAZ100E131 's pdf datasheet

AZ100E131 Pinout, Pinouts
AZ100E131 pinout,Pin out
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