ECL/PECL 1:4, 1:5 Differential Clock Driver

The AZ100LVE210 is a low skew 1:4, 1:5 fanout Buffer designed with Clock Distribution in mind. The device features fully differential Clock paths to minimize both device and system skew. The AZ100LVE210 offers two selectable Clock inputs allowing redundant or test Clocks to be incorporated into the system Clock trees. The AZ100LVE210 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For singleended input applications, the VBB reference should be connected to one side of the CLKa/CLKb differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB should only be used as a bias for its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor. Both sides of the differential output must be terminated into 50 to ensure that the tight skew specification is met, even if only one side is used. In most applications all eight differential pairs will be used and therefore terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 1020ps) of the outputs being used; while not being catastrophic to most designs this will result in an increase in skew. By Arizona Microtek, Inc.
AZ100LVE210 's PackagesAZ100LVE210 's pdf datasheet

AZ100LVE210 Pinout, Pinouts
AZ100LVE210 pinout,Pin out
This is one package pinout of AZ100LVE210,If you need more pinouts please download AZ100LVE210's pdf datasheet.

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