Low Voltage ECLinPS LITE 3V To 5.5V ECL Divide By 4 Divider

The AZ10LVEL33 AZ100LVEL33 is an integrated 4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q High) on the rising edge. Upon power-up, the internal Flip-Flop will be in a random Logic state. RESET allows for the synchronization of multiple LVEL33s in a system. The LVEL33 provides a VBB output for single-end use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the CLK/ CLK differential input pair. The input signal is then fed to the other CLK/ CLK input. The VBB pin CAN support 1.0mA sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor. By Arizona Microtek, Inc.
AZ100LVEL33 's PackagesAZ100LVEL33 's pdf datasheet
AZ10LVEL33
AZ100LVEL33NG
AZ10LVEL33D
AZ100LVEL33D
AZ10LVEL33T
AZ100LVEL33T




AZ100LVEL33 Pinout, Pinouts
AZ100LVEL33 pinout,Pin out
This is one package pinout of AZ100LVEL33,If you need more pinouts please download AZ100LVEL33's pdf datasheet.

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AZ100LVEL33 Application Notes AZ100LVEL33 RoHS AZ100LVEL33 Circuits AZ100LVEL33 footprint
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