Multiply By 16, 32 Phase-Locked Loop Clock Generator

The AZ12010 contains all of the functional elements necessary to implement a Phase-Locked Loop for Clock multiplication at frequencies up to 800 MHz. A fixed 32 times multiplication allows the use of low cost crystals or a low frequency reference signal. The output CAN be divided by two for 16 times net multiplication. The VCSO is differentially or single-ended driven using the chip CML SAW outputs. The dynamic properties of the PLL are under the control of the user through selection of the desired external components. By Arizona Microtek, Inc.
AZ12010 's PackagesAZ12010 's pdf datasheet

AZ12010 Pinout, Pinouts
AZ12010 pinout,Pin out
This is one package pinout of AZ12010,If you need more pinouts please download AZ12010's pdf datasheet.

AZ12010 Application circuits
AZ12010 circuits
This is one application circuit of AZ12010,If you need more circuits,please download AZ12010's pdf datasheet.

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