ECL/PECL ÷1, ÷2 Clock Generation Chip With Selectable Enable

The AZP92 is a specialized 1 or 2 Clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a 2 divider. A selectable enable is provided which also functions as a reset when the 2 mode is selected. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20k resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75k pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20k resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal 75k pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). This default Logic condition CAN be overridden by connecting the EN to VCC with an external resistor of 20k. Refer to the enable truth table on the next page for detailed operation. By Arizona Microtek, Inc.