The BCM8724 Ethernet LAN-PHY is a fully integrated dual- serialization/deserialization (10.3125 Gbps) Interface device performing the extension functions for a 10-gigabit serial Ethernet reconciliation sublayer (RS) Interface The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, Clock multiplication unit (CMU), and Clock and Data Recovery (CDR). On-chip Clock synthesis is performed by the high-frequency low-jitter phase-locked loops for the PMD and XAUI output retimers. Individual PMD and XAUI Clock recovery is performed on the device by synchronizing directly to their respective incoming data streams. Elastic Buffers are provided to allow the XAUI and PMD Interfaces to operate in asynchronous configuration. Only an external 156.25-MHz Oscillator is required for the reference Clock input. The serial 10-GbE receiver includes an adjustable equalizer/EyeOpener that allows for compensation for long trace lengths in multichannel linecard applications. The BCM8724 is available in a 19 mm x 19 mm, 324-pin FBGA with a 1.0-mm ball pitch RoHS compliant package. By Broadcom Corp.
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BCM8724 Application circuits
BCM8724 circuits
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