The BCM8752 is a dual-channel 10 GbE SFI-to-XFI (10-Gigabit serial electrical interface) PHY that incorporates an Electronic Dispersion Compensation (EDC) equalizer supporting SFP+ line-card applications. The BCM8752 is a multirate PHY targeted for optical fiber and copper twin-ax applications. It Interfaces with both limiting- and linear-based SFP+ and SFP modules, and SFP+ copper twin-ax cable. The BCM8752 is fully compliant with the 10 GbE SFP+ standard and also supports 1000BASE-X for 1 GbE operation. The BCM8752 is developed using an all-DSP high-speed front end, providing the highest performance and most flexibility for line-card designers. An on-chip Microcontroller implements the control algorithm for the DSP core. On-chip Clock synthesis is performed by the high-frequency, low-jitter, Phase-Locked Loops (PLLs). Individual Clock recovery is performed on the device by synchronizing directly to the respective incoming data streams. A single 156.25 MHz reference Clock input is required for the device. The BCM8752 Ethernet PHY is a fully integrated 10-Gigabit serial Ethernet retimer Interface The SFI, XFI, PCS, and PMA functions include 64B/66B coding, Clock Multiplication Unit (CMU), and Clock and Data Recovery (CDR). The BCM8752 is available in a 12 mm x 12 mm, 1 mm pitch, 121-pin BGA, RoHS-compliant package. By Broadcom Corp.
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BCM8752 Application circuits
BCM8752 circuits
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