Rad-Hard CMOS FIFO Register
CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage Register that CAN store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a Buffer between asynchronous systems.
Each word position in the Register is clocked by a control flip- flop, which stores a marker bit. A 1 signifies that the positions data is filled and a 0 denotes a vacancy in that position. The control Flip-Flop detects the state of the preceding Flip-Flop and communicates its own status to the succeeding Flip-Flop When a control Flip-Flop is in the 0 state and sees a 1 in the preceding Flip-Flop it generates a Clock pulse that transfers data from the preceding four data Latches into its own four data Latches and resets the preceding Flip-Flop to 0. The first and last control Flip-Flops have buffered outputs. Since all empty locations bubble automatically to the input end, and all valid data ripple through to the output end, the status of the first control Flip-Flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last Flip-Flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
By Intersil Corporation
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