CMOS Presettable Up/Down Counter

CD4029B consists of a four-stage binary or BCD-decade up/down Counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single Clock CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the Counter to any state asynchronously with the Clock A low on each JAM line, when the PRESET-ENABLE signal is high, resets the Counter to its zero count. The Counter is advanced one count at the positive transition of the Clock when the CARRY-IN and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT signal is normally high and goes low when the Counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state CAN thus be considered a Clock ENABLE. The CARRY-IN terminal must be connected to VSS when not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the Counter counts in the decade mode when the BINARY/DECADE input is low. The Counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages CAN be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17.
Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer Clock input rise and fall times.
The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
By Texas Instruments