64-stage Static Shift Register - National Semiconductor

The CD4031BM CD4031BC is an integrated, complemen- tary MOS (CMOS), 64-stage, fully static Shift register Two data inputs, DATA IN and RECIRCULATE IN, and a MODE CONTROL input are provided. Data at the DATA input (when MODE CONTROL is low) or data at the RECIRCU- LATE input (when MODE CONTROL is high), which meets the setup and hold time requirements, is entered into the first stage of the Register and is shifted one stage at each positive transition of the Clock Data output is available in both true and complement forms from the 64th stage. Both the DATA OUT (Q) AND DATA OUT (Q) outputs are fully buffered. The Clock input of the CD4031BM CD4031BC is fully buffered, and present only a standard input load capaci- tance. However, a DELAYED Clock OUTPUT (CLD) has been provided to allow reduced Clock drive fan-out and tran- sition time requirements when cascading packages. By National Semiconductor Corporation
CD4031BM 's PackagesCD4031BM 's pdf datasheet

CD4031BM Pinout, Pinouts
CD4031BM pinout,Pin out
This is one package pinout of CD4031BM,If you need more pinouts please download CD4031BM's pdf datasheet.

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