Cmos Dual 64-stage Static Shift Register Corporation

Cmos Dual 64-stage Static Shift register Corporation CD4517BMS dual 64-stage static shift Register consists of two independent Registers each having a Clock data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a Logic 1 and the Clock goes through a low-to-high transition. The truth table indicates how the Clock and write enable inputs control the opeation of the CD4517BMS. Inputs at the intermediate taps allow entry of 64 bits into the Register with 16 Clock pulses. The 3-state outputs permit connection of this device to an external bus. The CD4517BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6P By Intersil Corporation
CD4517BMS 's PackagesCD4517BMS 's pdf datasheet



CD4517BMS Pinout, Pinouts
CD4517BMS pinout,Pin out
This is one package pinout of CD4517BMS,If you need more pinouts please download CD4517BMS's pdf datasheet.

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