Dual J-K Flip-Flop With Reset Negative-Edge Trigger

The HC107 and CD74HCT107 utilize silicon Gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These ip-ops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the Clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT Logic family is functionally as well as pin compatible with the standard LS family. By Texas Instruments
Part Manufacturer Description Datasheet Samples
CD54HC107F3A Texas Instruments High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125
CD54HC107 's PackagesCD54HC107 's pdf datasheet
CD54HC107F3A




CD54HC107 Pinout, Pinouts
CD54HC107 pinout,Pin out
This is one package pinout of CD54HC107,If you need more pinouts please download CD54HC107's pdf datasheet.

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