Dual Positive-Edge-Triggered J-K Flip-Flops With Set And Reset

The CD74AC109 devices contain two independent J-K positive-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the Clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the Clock pulse. Following the hold-time interval, data at the J and K inputs CAN be changed without affecting the levels at the outputs. These versatile Flip-Flops CAN perform as toggle Flip-Flops by grounding K and tying J high. They also CAN perform as D-type Flip-Flops if J and K are tied together.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CD74AC109E Texas Instruments Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
CD74AC109M96G4 Texas Instruments AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
CD74AC109M96E4 Texas Instruments AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
CD74AC109M96 Texas Instruments Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
CD74AC109EE4 Texas Instruments Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
CD74AC109 's PackagesCD74AC109 's pdf datasheet
CD74AC109E PDIP
CD74AC109EE4 PDIP
CD74AC109M96 SOIC
CD74AC109M96E4 SOIC
CD74AC109M96G4 SOIC




CD74AC109 Pinout, Pinouts
CD74AC109 pinout,Pin out
This is one package pinout of CD74AC109,If you need more pinouts please download CD74AC109's pdf datasheet.

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