Presettable Synchronous 4-Bit Binary Up/Down Counter

The CD74AC191 and CD74ACT191 are asynchronously presettable binary up/down synchronous Counters that utilize the Harris Advanced CMOS Logic technology. Presetting the Counter to the number on preset data inputs (P0-P3) is accomplished by setting LOW the asynchronous parallel load input (PL). Counting occurs when PL is HIGH, Count Enable (CE) is LOW, and the Up/Down (U/D) input is either LOW for up-counting or HIGH for down-counting. The Counter is incremented or decremented synchronously with the LOW-to-HIGH transition of the Clock When an overow or underow of the Counter occurs, the Terminal Count (TC) output, which is LOW during counting, goes HIGH and remains HIGH for one Clock cycle. This out- put CAN be used for look-ahead carry in high-speed cascad- ing (see Figure 12). The TC output also initiates the Ripple Clock (RC) output which, normally HIGH, goes LOW and remains LOW for the low-level cascaded using the Ripple Count output. By Texas Instruments
CD74AC191 's PackagesCD74AC191 's pdf datasheet
CD74AC191E PDIP
CD74ACT191E PDIP
CD74AC191M SOIC
CD74ACT191M SOIC




CD74AC191 Pinout, Pinouts
CD74AC191 pinout,Pin out
This is one package pinout of CD74AC191,If you need more pinouts please download CD74AC191's pdf datasheet.

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