High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops With Set And Reset

The CD74HCT112 and ?HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These Flip-Flops have independent J, K, Set, Reset, and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the Clock pulse. Set and Reset are accomplished asynchronously by low-level inputs.
The HCT Logic family is functionally as well as pin-compatible with the standard LS Logic family.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CD74HCT112E Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
CD74HCT112EE4 Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
CD74HCT112 's PackagesCD74HCT112 's pdf datasheet
CD74HCT112E PDIP
CD74HCT112EE4 PDIP




CD74HCT112 Pinout, Pinouts
CD74HCT112 pinout,Pin out
This is one package pinout of CD74HCT112,If you need more pinouts please download CD74HCT112's pdf datasheet.

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